VSPOL=Val_0x0, HSPOL=Val_0x0, BLPOL=Val_0x0, PCLKPOL=Val_0x0
Global Control Register
| CDC_EN | Global enable. Mirrored to pin CDC_DE. The display controller can be globally enabled/disabled. If the display controller is disabled, the timing generator is reset to X = total_width - 1, Y = total_height - 1, and held. Thus only blanking data is output continuously while the display controller is disabled and no new bus accesses are started. Outstanding read data is discarded and the FIFOs are flushed. The value is mirrored to pin CDC_DE. |
| GAMMA_EN | Gamma correction enable. When it is disabled, the RGB data bypasses the gamma correction CLUT. |
| DITHER_B | Dither bits blue (0-4). Dither bits width for blue color component. |
| DITHER_G | Dither bits green (0-4). Dither bits width for green color component. |
| DITHER_R | Dither bits red (0-4). Dither bits width for red color component. |
| DITHER_EN | Dithering on. Dithering can be enabled/disabled. A 4x4 Bayer pattern is added to each color component. |
| PCLKPOL | Output pixel clock polarity. Signal polarity: 0 (Val_0x0): Feed-through of PIXEL_CLK input 1 (Val_0x1): Inverted PIXEL_CLK input |
| BLPOL | Blank polarity. Signal polarity: 0 (Val_0x0): Active low 1 (Val_0x1): Active high |
| VSPOL | VSync polarity. Signal polarity: 0 (Val_0x0): Active low 1 (Val_0x1): Active high |
| HSPOL | HSync polarity. Signal polarity: 0 (Val_0x0): Active low 1 (Val_0x1): Active high |